With continual scaling of semiconductor devices in each new generation, semiconductor technologies face challenges in circuit design and processing technology. Circuits with complex wiring pose additional challenges since wiring of semiconductor devices is constrained by lithographic limitations.
For example, conventional static random access memory (SRAM) devices require complex wiring even at an M1 level (the first metal wiring level above a semiconductor substrate) since the internal nodes of an SRAM cell need to be connected at the M1 level. The use of the M1 level for internal node wiring forces the wiring of the bit lines into an M2 level (the second wiring level above the semiconductor substrate) and the wiring of word lines into an M3 level (the third wiring level above the semiconductor substrate). For conventional SRAM circuits, power buses are thus typically used only in an M4 level and above.
It is advantageous, however, to use a reduced number of wiring levels for a circuit and to minimize the wiring lengths since interconnect wires in each wiring level are capacitively coupled to adjacent interconnect wires, wiring vias, contact vias, and/or gate electrode lines. In the case of SRAM devices, the internal node connection at an M1 level and the bit lines and word lines at M2 and M3 introduce parasitic capacitance between the interconnect wires in each wiring level and other interconnect structures nearby.
Further, other semiconductor devices in general may employ a local interconnect containing an M1 wire to electrically connect a polysilicon conductor (PC) level conductive structure, such as a gate top silicide, to an active area (AA) level conductive structure, such as a source and drain silicide. PC level refers to the level of gate conductors and AA level, or recessed oxide (RX) level as it is alternatively called, refers to the level of the top surface of the source and drain in conventional planar metal-on-semiconductor (MOS) transistors. Such a local interconnect between the PC level and the AA level requires contact array (CA) level contact vias as well as the M1 wire. This approach in general adds at least three wiring components, i.e., two contact array (CA) level contact vias and one M1 wire to each local interconnect, and thus adds substantial parasitic capacitive coupling to the device components nearby as well as occupying a volume of the M1 level that may not be utilized for other wiring. Further, the two conductive structures that are electrically connected by the local interconnect need to be separated at least by a minimum distance between the two adjacent CA contact vias imposed by lithographic constraints, which is typically on the order of the diameter of the CA contact vias. To electrically connect three or more conductive components, more CA contact vias are employed.
Alternatively, contact array bars (CA bars) in the shape of a cylinder with a substantially oval cross-sectional area and formed in the CA level are employed to connect two adjacent conductive structures between the PC level and the AA level. While capable of providing a local interconnection between a PC level conductive structure and an AA level conductive structure, a local interconnect with a CA bar requires that the two conductive structures are located within the cross-sectional area of the CA bar, and substantially abutting or almost abutting each other. Therefore, CA bars do not provide a local interconnect solution to a pair of conductive structures in the PC level or in the AA level that are separated by a distance longer than the horizontal dimensions of a CA bar. Moreover, it is difficult to produce both circular shaped CA and oval shaped CA bar together due to the fact they require different illumination conditions during printing step and they have different etch bias during etch step. The appearance of various shapes on one level reduces process window significantly.
Referring to FIG. 1A-1C, an exemplary prior art SRAM structure comprises a first pull-up PFET 16, a second pull-up PFET 16′, two pull down NFETs (14, 14′), and two pass gate NFETs (12, 12′). FIG. 1A is a top-down view of the exemplary prior art structure up to the CA level not showing a middle-of-line (MOL) dielectric 70. FIG. 1B is a vertical cross-sectional view of the exemplary prior structure along the plane B-B′ showing the MOL dielectric 70. FIG. 1C is a vertical cross-sectional view of the exemplary prior structure along the plane C-C′ showing the MOL dielectric 70. Each of the transistors (12, 12′, 14, 14′, 16, 16′) comprise a portion of the semiconductor substrate 10, a gate dielectric 30, a gate conductor 32, a gate spacer 34, active area (AA) silicides 60, and gate top silicides 64. Shallow trench isolation 20 physically separates the transistors (12, 12′, 14, 14′, 16, 16′) and provides electrical isolation among the transistors (12, 12′, 14, 14′, 16, 16′). CA contact vias 76 and CA bars 78 are employed to provide electrical wiring among the transistors (12, 12′, 14, 14′, 16, 16′). One of the CA bars 78, which contacts one of the AA silicides 60 of the first pull-up PFET 16 as well as the gate top silicides 64 of the second pull-up PFET 16′ as shown in FIG. 1B, provide electrical connection between the drain of the first pull-up PFET 16 and the gate of the second pull-up PFET 16′. Likewise, another CA bar 78 provides electrical connection between the drain of the second pull-up PFET 16′ and the gate of the first pull-up PFET 16.
Referring to FIGS. 2A-2C, the exemplary prior art SRAM structure is shown up to the M1 level. FIG. 2A is a top-down view of the exemplary prior art structure up to the M1 level not showing the middle-of-line (MOL) dielectric 70 and an M1 dielectric 80. FIG. 2B is a vertical cross-sectional view of the exemplary prior structure along the plane B-B′ showing the MOL dielectric 70 and the M1 dielectric 80. FIG. 2C is a vertical cross-sectional view of the exemplary prior structure along the plane C-C′ showing the MOL dielectric 70 and the M1 dielectric 80. M1 wires 88 embedded within the M1 dielectric 80 contact the underlying CA contact vias 76 and the CA bars 78. In the exemplary prior art SRAM structure, FIGS. 2A and 2C illustrate that the drain of each of the two pull-up transistors (16, 16′) is electrically connected to a node at which a source/drain of one of the pass gate transistors (12, 12′) adjoins the drain of one of the pull-down NFETs (14, 14′) by a combination of a CA bar 78, an M1 wire 88, and a CA contact via 76. Two such combinations are present in each SRAM cell structure which comprises six transistors (12, 12′, 14, 14′, 16, 16′).
Referring to FIG. 3, a circuit schematic 18 for the exemplary prior art SRAM structure shows a first pair of a first pass gate n-type field effect transistor (NFET) 2 and a first pull-down n-type field effect transistor (NFET) 4 wherein a first source/drain of the first pass gate NFET 2 and a first drain of the first pull down NFET 4 are adjoined to form an electrical connection. In the physical structure, this electrical connection is achieved by a first common active area that contains both the first source/drain of the first pass gate NFET 2 and the first drain of the first pull-down NFET 4. Similarly, a second source/drain of the second pass gate NFET 2′ and a second drain of a second pull-down NFET 4′ are adjoined to form another electrical connection. In the physical structure, this electrical connection is achieved by a second common active area that contains both the second source/drain of the second pass gate NFET 2′ and the second drain of the second pull-down NFET 4′. The circuit schematic 18 further comprises a first pull-up p-type field effect transistor (PFET) 6 containing a third drain, which is physically a third active area, and a second pull-up PFET 6′ containing a fourth drain, which is physically a fourth active area. Each of the source/drain nodes of the pass gate transistors (2, 2′) may function as a source or a drain depending on the operation of the SRAM circuit.
According to the prior art, the third active area is electrically connected to the first active area via a collection of a first contact via, a first M1 wire, and a first CA bar. This connection is represented in the circuit schematic 18 by a first internal node 11. Similarly, the fourth active area is electrically connected to the second active area via a collection of a second contact via, a second M1 wire, and a second CA bar. This connection is represented in the circuit schematic 18 by a second internal node 11′. The gates of the second pull-up PFET 6′ and the second pull-down NFET 4′ are adjoined to the third drain of the first pull-up PFET 6 via the first CA bar. This connection is represented in the circuit schematic 18 by a third internal node 13A and a fourth internal node 13B. The gates of the first pull-up PFET 6 and the first pull-down NFET 4 are adjoined to the fourth drain of the second pull-up PFET 6′ via the first CA bar. This connection is represented in the circuit schematic 18 by a fifth internal node 13A′ and a sixth internal node 13B′.
According to the prior art, the internal nodes (11, 11′, 13A, 13B, 13A′ 13B′) are connected by CA contact vias 76 and CA bars 78 as well as M1 wires 88. The use of the M1 wires blocks substantial area at the M1 level from being utilized for other wiring purposes. Therefore, both the bit line wiring (15, 15′) and word line wiring (17, 17′) need to be implemented above the M1 level not to lose area efficiency in an SRAM design. Further, substantial inter-level capacitance is introduced by the use of M1-M3 levels in the SRAM structure according to the prior art.
In summary, prior art local interconnect methods between two conductive components within the PC level and the CA level have severe limitations in terms of the proximity between the two components. CA bars provide a local interconnect only between an adjacent pair of a PC level conductive structure and an AA level conductive structure separated by a distance less than the dimension of the CA bars, which is at most about twice the diameter of a CA contact via. A local interconnect employing a combination of CA contact vias and an M1 wire requires a minimum separation between the two interconnected structures, typically by a distance greater than the diameter of a CA contact via. More importantly, the M1 wire occupies a volume in M1 level, preventing the use of the volume for other M1 level wiring structures. Further, the prior art local interconnect methods also introduce parasitic capacitance between the local interconnect structure and other semiconductor components. In the case of the exemplary prior art SRAM structure discussed above, the local interconnect structures that connect internal nodes, specifically the local interconnect structures that connects each of the pass gate transistors to the drains of one of the two pairs of a pull-up PFET and a pull-down NFET, occupies the M1 level, making utilization of the M1 level for bit line wiring impractical, and also increasing the parasitic capacitance of the internal nodes.
Therefore, there exists a need for a local interconnect structure that connects a pair of at least two conductive structures in the PC level and/or in the AA level that does not occupy a space in an M1 level and methods of manufacturing the same.
Furthermore, there exists a need for a local interconnect structure for an SRAM in which internal nodes may be wired without utilizing M1 level wiring and methods of manufacturing the same.